1. Field of the Invention
The present invention relates to a semiconductor circuit device and more particularly to a semiconductor circuit device receiving an external power supply voltage and having normal and test modes.
2. Description of the Background Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) is currently provided as a semiconductor circuit device. Recently, a semiconductor memory device having an internal power supply circuit which generates an internal power supply voltage (3.3V, for example) by lowering an external power supply voltage (5V, for example) has been also provided to reduce power consumption.
FIG. 14 is a circuit diagram showing a structure of a conventional internal power supply circuit used, for example, in a DRAM. Referring to FIG. 14, the conventional internal power supply circuit includes a differential amplifier 3 and a driver transistor 4. Differential amplifier 3 has an inverted input terminal receiving a reference voltage VREF and a non-inverted input terminal connected to an internal power supply node 2. Driver transistor 4 has its gate connected to an output terminal of differential amplifier 3, and it is connected between an external power supply node 1 and internal power supply node 2.
In the above described internal power supply circuit, the internal power supply voltage intVCC is fed back to differential amplifier 3, thus differential amplifier 3 controls driver transistor 4 so that internal power supply voltage intVCC equals to the reference voltage VREF. That is, differential amplifier 3 and driver transistor 4 form a closed loop. As a result, this internal power supply circuit supplies internal power supply node 2 with internal power supply voltage intVCC lower than the external power supply voltage extVcc.
In the above described internal power supply circuit, driver transistor 4 has desirably wider gate width to supply much current to internal power supply node 2. This is because, as shown in FIG. 15, drivability of driver transistor 4 improves as the gate width (W) becomes wider.
However, since a feedback loop is formed in the internal power supply circuit as described above, stability to oscillation degrades as driver transistor 4 has a wider gate width (W). Thus, there is a so-called trade-off between the drivability of driver transistor 4 and the stability to oscillation.
Therefore, the gate width (W) of driver transistor 4 is desirably designed to be the widest as long as oscillation is not caused. However, unexpected oscillation may occur after fabrication of a DRAM chip because it is difficult to perfectly predict an optimal gate width (W) having high drivability and improved stability to oscillation through, for example, simulation. Also, variation in a manufacturing process may cause oscillation.
When oscillation occurs after fabrication of the DRAM chip as above, the gate width (W) of a driver transistor must be redesigned to be narrower. However, it is difficult to predict how narrow a gate width (W) is sufficient to stop oscillation. Therefore, oscillation may occur again even if a new chip is fabricated by revising a mask. Thus, repetition of mask revision has been required to optimally design the gate width of driver transistor 4.
Although the FIB (Focused Ion Beam) process may evaluate the optimal gate width (W) to reduce repetition of mask revision, it is troublesome. Also, oscillation may occur inspite of the FIB process beforehand.